MTS Silicon Design Engineer
Advanced Micro Devices
Markham, Ontario, CA
12h ago

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

MTS Silicon Design Engineer


As part of SOC (System-On-Chip) DFX team you will be involved in design, integration, verification & timing analysis for state-of-the-art design-for-test and design-for-debug features in complex AMD products.

You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification and emulation of those features until deliveries to PEO (product engineering organization) and debug on ATE (automated test equipment)


  • Should have strong problem-solving skills
  • Good English hearing, speaking, reading and writing capabilities and good communication skills

  • Hands-on working experience on ASIC design and / or verification and / or testing / validation
  • Should have strong problem-solving skills
  • Experience with microprocessor design is a plus
  • Knowledge of scripting programming languages (TCL, Perl) is a plus.
  • Knowledge of C++, System Verilog, UVM verification methodology is a plus
  • Experience in complex ASIC design in DFT / DFD techniques such as JTAG / IEEE standards, scan and ATPG, on-chip scan pattern compression and at-speed testing using PLL, memory BIST and repair, power-gating, on-chip debug logic is a big plus but is not a must-have requirement

    The qualified candidate will work as part of Design-For-Test (DFT) team to perform some or all the below functions :

  • Implement SCAN Insertion for different IPs in state of the art SoC chips
  • Perform ATPG (automatic test pattern generation) for IPs and SoCs.
  • Run ATPG patterns simulations and perform debug of the failures.
  • Participate in ATPG patterns bring-up on ATE (Automatic Test Equipment) when the first silicon is back.

  • BS in EE & CS
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