Physical Design Engineer
Talentlab
Toronto, ON, Canada
4d ago

Our client is looking to add a Physical Design Engineer to their high performing team!

What is needed to succeed?

  • Generate Verilog net list from RTL and block level and top level chip constraints from a functional spec.
  • Performing Static Timing Analysis (STA) at the chip level.
  • Hierarchical floor planning. IR drop analysis.
  • Hierarchical physical layout to include clock tree design and distribution. Hierarchical timing closure to include fixing setup and hold violations.
  • Signal Integrity analysis and physical verification.
  • Do you have?

  • Bachelors degree in Electrical Engineering with 1-3 years experience
  • Experience with Synopsys, Physical Compiler, PrimeTime, and custom layout tools
  • Experience with DRC / LVS tools
  • Good documentation and presentation skills.
  • The ability to work with software, hardware, and verification engineers.
  • Possess the ability to collaborate with technical peers,
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