Design for Test Engineer - Central DFT.
Markham, Ontario, CA
3d ago

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Design for Test Engineer - Central DFT

The Role :

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia.

It is primarily responsible for architecture, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for leading edge AMD products.

It is also responsible for DFX design methodology and automation tools development to support the global DFX engineering teams across AMD.

The Person :

As a Silicon Design Engineer, you will be working with a diverse team of design engineers and managers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives.

This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

The following highlights a successful candidate :

  • Demonstrated DFT design skills and project execution experience
  • Excellent verbal and written communication and interpersonal skills
  • Self-starter, driven and disciplined with a dedication to meeting deadlines
  • Has an aptitude to thrive in a fast-paced multi-tasking environment
  • Used to working independently, and yet can work collaboratively with various levels and organization functions.
  • Key Responsibilities :

  • Working with a multi-discipline and international team of engineers on design-for-test (DFT) architecture, design, tools and methodology initiatives
  • Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
  • Performing scan insertion, ATPG verification and test pattern generation
  • Writing and maintain DFT documentation and specifications
  • Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints
  • Performing DFT RTL design per micro-architectural specifications using design generation flows
  • Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis
  • This job also involves using the test automation software for data collection one week per year at one of the USA national laboratories
  • Preferred Experience :

  • Demonstrated ASIC design experience
  • Demonstrated technical leadership and works well with cross-functional teams
  • Excellent communication and interpersonal skills
  • Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential
  • Experience in complex ASIC design (multi-million gates) in DFT / DFD techniques such as JTAG / IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
  • Understanding various technologies that must work with DFT / DFD technology such as CPU’s, graphics engines, high-speed digital design, memory and I / O controllers, etc
  • Working knowledge and experience in verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
  • Experience in solving logic design or timing issues with integration, synthesis and PD teams
  • Good working knowledge of UNIX / Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
  • Knowledge in EDA tools / methodology, such as synthesis, equivalency checking, static timing analysis
  • Knowledge of ATE and digital IC manufacturing test is a plus
  • Knowledge in using emulator for ATPG pattern verification is a plus
  • Academic Credentials :

  • Minimum B.Sc in Electrical or Computer Engineering (or equivalent)
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