Summer 2020 Digital Verification Engineering Intern
Synopsys, Inc
CANADA - Canada
6d ago

Job Description and Requirements

Digital Verification Engineering Intern

Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars.

Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything where devices are getting smarter, everything’s connected, and everything must be secure.

Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them.

Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.

Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems.

To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems.

Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Seeking a highly motivated and innovative digital verification engineer with strong theoretical and practical background in high-

speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2 / 3 SERDES products.

The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Starting in May 2020, this 16-month internship position will be with our Solutions Group in Mississauga .

What you will learn :

  • Excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-
  • end mixed-signal designs

  • Writing constrained-random SystemVerilog testbenches using UVM and VMM
  • Creating and analyzing functional coverage and assertion coverage, and analyzing code coverage
  • Defining and tracking verification testplans
  • Debugging RTL and gate-level simulation failures
  • SystemVerilog analog behavior modelling
  • Skill Requirements :

  • Experience writing scripts in languages such as Perl and Unix shell
  • Familiar with Verilog and SystemVerilog
  • Education Requirements :

  • Enrolled in Computer Engineering or Electrical Engineering program, or similar
  • Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

    Should you require an accommodation, please contact .

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