Inphi is seeking an Analog & Mixed-Signal Design Engineer to contribute to the development of multi-tens of GHz Analog equalization or DSP equalization based transceivers.
These advanced transceivers consist of broad-band channel equalization circuitries. Our DSP based Clock-Data-Recovery solutions consists of 10s of GHz ADC / DAC and employ Inphi’s innovative technologies to address the extreme challenges in low-jitter clock generation and distribution.
The results of these innovative work enable Inphi to produce the world’s first single-chip 100Gb / s (2x50G) PAM4 DSP transceiver (2015), world’s first single-chip 200Gb / s (4x50G) DSP based PAM4 transceiver (2018) and world’s first single-chip 400Gbps (4x100G) in advanced CMOS nodes.
MSc / PhD EE in the areas of design of high-performance analog / mixed-signal ICs.
Proven experience in IC design including chip tape-out AND lab evaluation of design (either during graduate studies or working in the industry). Solid experience in
Using EDA CAD tools
Performing Analog Custom Layout
Experience in measuring IC performance and debug of design to correlate simulations to measurements
Deep understanding of fundamental, including :
Detailed transistor level design
Control / Feedback loop stability analysis
Direct project experience in at least one of the following areas a plus : ADC-DAC designPLL or clock / freq generation designRF / High-Speed (10GHz+) issues
Knowledge & experience in Verilog coding a plus
Experience in Package-System integration issues desired
Project experience in using advance CMOS nodes (FinFET experience a plus)
Strong communication, presentation and documentation skills.