In this role, you will be working in a team environment conducting research and development into next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY, HSS, wireline transceivers, optical transceivers) in deep submicron FinFET technologies.
Multiple positions are available at differing seniority levels (Junior to Principal) depending on candidate qualifications.
You will be responsible for silicon validation and application engineering activities for large analog and mixed signal systems.
In this role you will work in a new state of the art SerDes validation testing laboratory currently under construction at the Huawei Toronto Research Center and will interact directly with teams in Canada and abroad.
You will put into action your solid understanding of wireline transceiver fundamentals to create and execute plans that meet program requirements and customer commitments in the following areas :
Lead timely delivery of validation test reports, characterization and reliability test reports, firmware releases, and customer documentation (datasheet, programming guide) releases
Provide regular program status communication to technical managers and customers
Align application engineering and validation test best practices across company locations
Collaborate with analog / system / digital design engineers, package and PCB engineers, and software engineers to ensure efficient silicon bring-
up and early silicon test results
Support global product teams from requirements definition through to mass production
Promote high-speed interface solutions to customers through the organization of on-site demos
PHD, MASc. or BASc in Electrical Engineering or equivalent degree
PHD, or 4 years + MASc, or 10 years + BASc of relevant experience in application and test engineering
Must have recent hands on experience in
Must have : customer support or application engineering experience
Experience in production test and yield enhancement is an asset
Experience in optical communication, silicon photonics, or package design is an asset
Knowledge of signal integrity and power integrity concepts is an asset
Familiarity with Matlab and programming languages (C / C++, C#, Python) is an asset
Must have : experience with 15Gbps+ test equipment (oscilloscope, JBERT, VNA, etc.)
Compensation Package Highlights
Competitive Salary, Bonuses, and Group R.R.S.P
Comprehensive Benefits Packages- (Dental, Vision, and Medical)
Short and Long-term Disability Insurance