ASIC Physical Design Engr, Sr II
Synopsys, Inc
CANADA - Ontario - Nepean
3d ago

Job Description and Requirements

Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars.

Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything where devices are getting smarter, everything’s connected, and everything must be secure.

Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them.

Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.

Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

Founded in 1986, $2.6B+ Synopsys employs 11,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, and India.

Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. We’re also committed to partnering with the communities in which we work.

Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.

Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!

Physical Design Engineer

The role you will be primarily responsible for, but not limited to the following :

  • Participating in complex block and / or chip planning and architecture studies;
  • Interfacing with front-end design engineers to guide & assist with design styles, synthesis choices, physical layout planning, and DFT planning;
  • Assist project design team in defining initial floorplan estimates such as die size, block placement, number of required routing layers, power grid planning, and data flow;
  • Developing & testing methods to deal with power & signal integrity issues on a per-project basis;
  • Setup various EDA tools used for the physical design flow;
  • Create & maintain physical chip floor plan;
  • Guide full-custom layout & design groups in proper generation of macro cells for ASIC environment;
  • Use manual & automated approaches to placing core cells, creating clock & buffer trees, perform timing optimization, and chip routing;
  • Implementation and verification of DFT (logic scan, boundary scan, BIST, ATPG);
  • Perform RC extraction (estimated and detailed), delay calculation, STA, and timing analysis;
  • Perform power grid integrity analysis and signal integrity analysis.
  • Furthermore, you will assume responsibility for design timing closure; create post-layout netlists, perform equivalency checking;
  • assist full-custom layout group with final DRC / LVS / ERC / visual audits; assume responsibility for correct silicon implementation of block(s) / chip while adhering to the project schedule;
  • provide documentation of various aspects of design implementation, such as DFT structures. You may also be required to communicate (e-

    mail, fax, voice, meeting) with customers regarding technical issues.

    The successful candidate will have a strong desire to learn and explore new technologies, demonstrate good analysis and problem-

    solving skills and will have prior knowledge and experience of CAD tool development.

    Typically, this role will require a BSEE with a minimum of 5+ years of related experience and a candidate who possesses a full understanding of specialization area plus working knowledge of multiple related areas, will resolve a wide range of issues in creative ways and exercises judgment in selecting methods and techniques to obtain solutions.

    Furthermore, this position will perform in a project leadership role and will contribute to complex aspects of a project while receiving little to no instructions on day-

    to-day work though will occasionally receives general instructions on new assignments and projects. Work is independent and collaborative in nature and it is expected that regular updates will be provided to manager on project status.

    The successful candidate will represent the organization on business unit and / or company-wide projects, will guides more junior peers with aspects of their job and will frequently networks with senior internal and external personnel in own area of expertise.

    Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

    Should you require an accommodation, please contact .

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