As a Senior SerDes Physical Implementation Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56 / 112G PAM4 standards.
The Mixed-Signal IP organization is seeking a motivated person responsible for the physical implementation of complex Mixed signal IPs and testchips across multiple process technologies with a specific focus on very advanced high speed SERDES platforms.
In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.
The successful candidate will have the following :
10 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and / or project head.
Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.
And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.
The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
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