IP Design Verification Manager- 99263
Advanced Micro Devices
Markham, Ontario, CA
1d ago

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Title : IP Design Verification Manager

The Role :

We are currently looking for IP Design Verification Manager for IOMMU team. The IOMMU team (inside NBIO organization) is all about leading-edge I / O technologies.

From developing high-speed next-generation PCIe and USB interconnects, to I / O virtualization technologies powering data center and machine learning work loads, these IPs touch all AMD products CPUs, Graphics cards, and Game consoles.

This team is part of the bleeding edge of development for tomorrow’s client, server, embedded, graphics, and semi-custom chips.

As a verification manager, you will lead a team of verification engineers and work on IP level functional verification and its closure for IOMMU IP.

The Person :

  • Will demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail
  • Will have good communication and writing skills
  • Will have good teamwork and interpersonal skills
  • RESPONSIBILITIES :

  • Drive development of IP level verification testbench architecture, test methodology, and automated verification infrastructure
  • Lead development and debugging of functional models and test plans using SystemVerilog / UVM / C++ constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement / maintain testbenches and tests
  • Manage regression result triaging, test debug, and coverage analysis, and resolve technical issues with design, verification, and other teams, to improve verification metrics
  • Coordinate resolution of IP integration issues with SoC Integration, SoC DV and post-silicon validation teams
  • Collaborate with project management and other team leads on verification delivery against the project milestone requirements and verification metrics
  • Collaborate with other technical leads on process, methodology, and technical enhancements to design verification, to drive continuous improvement and positive changes
  • Preferred Experience & Skill sets :

  • Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture
  • Prior technical management experience is a plus asset
  • Extensive hardware verification experience
  • Experience and understanding of logic IP for virtualization in computer systems
  • Familiarity with industry-standard high-speed protocols and Controller IP such as PCI Express (PCIe)
  • Must be proficient in Verilog, System Verilog, C and C++, UVM, and working in Linux and Windows environments
  • Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
  • Must have excellent programming skills
  • Must demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail.
  • Education : Electrical or Computer Engineering

    Location : Markham, ON

  • LI-AP1
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