Display IP Design Verification Engineer - 77718
Advanced Micro Devices
Markham, Ontario, CA
4d ago

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Display IP Design Verification Engineer

THE ROLE :

The Display Controller team within the Radeon Technologies Group(RTG) is looking for an individual to participate in the design verification of the Display IP.

THE PERSON :

The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system.

The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration.

Experience with hardware modeling, assertions, and formal verification methods are valuable assets. The candidate would be expected to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within aggressive, market-driven schedules.

KEY RESPONSIBILITIES :

  • Join in the development of leading-edge display technologies and understand the architecture of the Display IP and functional blocks being designed.
  • Use advanced verification methodologies for the verification of complex designs
  • He / she is expected to own and execute on the verification of a sizable design by applying UVM verification methodology
  • Work with existing tools / flows or develop new tools / flows to complete the assigned verification task.
  • Compose test and coverage plan, and validation vectors to ensure functional completeness
  • Build SystemVerilog and / or C / C++ models and test sequence libraries for simulation
  • Build test bench and monitors for DUT
  • Debug function / performance bugs of Display IP
  • ACADEMIC CREDENTIALS :

  • Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.
  • LI-EM1

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