To work on analog and mixed signal blocks or system, for high speed SerDes or PHY designs
Candidate may also have the task of leading on certain technical aspects of the whole system in consultation with senior team members inside and outside the analog team
Work closely with cross-functional and offshore circuit design engineers and architects, on a larger design project
Should have strong analog design fundamentals
Experience in designing analog circuit blocks viz. PLL, data-converters, voltage regulators, crystal oscillators, continuous filters etc.
and preferably with experience in designing high-speed SerDes or PHY blocks (viz. continuous-time equalizers, DFE, CDR, PLL, Line driver, etc.
in deep sub-micron planar / FinFET technology
Experience with analog tools (viz. Virtuoso, Spectre, ADE and post layout extraction tools) is a must
Experience in high-speed PHY designs, along with core experience in analog-mixed signal designs, is a plus
Should have good understanding of analog layouts and its effect on high-speed designs
Track record of designing high volume products in advanced processes
Experience in system level pre-tape out analog validation
Experience in lab chip bring-up and debugging efforts is desirable
Technical management experience is a plus
Education & Experience : BSEE with minimum 8+ experience or MSEE with minimum 7+ years in Analog Circuit Design