Silicon Design Engineer 2- 115086
AMD
Markham, Ontario, CA
6d ago

THE ROLE :

As part of SOC (System-On-Chip) DFX team you will be involved in design, integration, verification & timing analysis for state-of-the-art design-for-test and design-for-debug features in complex AMD products.

You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification and emulation of those features until deliveries to PEO (product engineering organization) and debug on ATE (automated test equipment)

THE PERSON :

  • Must have excellent written and verbal communication skills
  • Must excel in a dynamic team working environment
  • Leadership and mentoring skills a definite asset
  • Must be a self-starter and be able to independently drive tasks to completion
  • Ability to be flexible in terms of responsibilities
  • KEY RESPONSIBILITIES :

    The successful candidate will report to the SOC DFT (Design-For-Test) Integration & Design Verification Manager and will have the following responsibilities :

  • Develop RTL and integrate internal / external RTL logic into SoC (System-On-Chip)
  • Write and review verification test-plans
  • Develop verification infrastructure, test-bench components and test-cases
  • Drive performance verification on all DFT structures
  • Generate and verify DFT structural patterns and functional patterns
  • Participate in ATE bring-up and debug the DFT patterns on ATE and platform
  • PREFERRED EXPERIENCE :

  • Knowledge of Verilog, C / C++ and scripting languages; experience with Perl and TCL is a plus
  • Familiar with entire ASIC design flow, hands on working experience on ASIC DFT design and verification is an advantage
  • Knowledge of UVM and OVM verification methodologies is an advantage
  • Strong analytical / problem solving skills and pronounced attention to details.
  • Experience in complex ASIC design (multi-million gates) and in DFT / DFD techniques such as JTAG / IEEE standards, Scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic is a plus
  • Experience in verification of multiple PHY protocols such as PCIE, XGMI, WAFL, GDDR6, USB2 / 3.1 and Display port is a plus
  • ACADEMIC CREDENTIALS :

  • BS or higher in EE & CS
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