What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.
It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.
If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Title : : Analog Designer
The Role :
The I / O Pad Ring Team is looking for a candidate to perform I / O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today.
I / O Pad Ring refers to the input / output interfaces that are found in a ring around the chip. Interfaces like USB, HDMI, PCIE, GPIO all reside in the IO Pad Ring.
This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer.
CPU / GPU / APU and semi-custom AMD's products featured in Sony Playstation and Microsoft Xbox, to name a few. It is a very exciting environment and you will be working with the very best in our technology.
The Person :
The candidate should have very good problem solving / debug skills and be able to see through the latter stages of a product delivery.
Strong communication skills will also be beneficial for this role
Day to day responsibilities include, assembly of macros / IPs / RDL into an I / O pad ring database, and then running various verification tools on that assembled database to determine integration issues.
If issues are discovered, communication with various IP owners may be required to facilitate issue resolution. Some of these include DRC, LVS, ERC and Latch up / ESD.
Prior experience training and leading junior resources preferred. Construction of product I / O pad rings using established flows and scripts.
Generated views include : Verilog, Def, Spice, and GDSII.
Physical verification on designs that contain up to 200M devices including : LVS, DRC, ERC and PERC. Delivery of all needed waivers(ERC / DRC / EDRC / PERC) and documentation to SoC teams
Facilitate ESD and design reviews for 3rd party IPs and I / O ring Tracking of IP versions, visual inspections and in-context XOR verifications.
Preferred Skilled Sets :
Strong understanding of physical verification checks (LVS / DRC / ERC / PERC), and ability to debug and resolve issues.
Must have detailed knowledge of CMOS circuit theory. Ideal candidate will have experience in the 16nm / 14nm / 7nm space.
Knowledge of chip level integration and ESD / LUP concepts.
Must have ability to communicate with various teams to articulate issues, requirements and drive the solutions.
Physical verification experience using Mentor Calibre (LVS, DRC, PERC), and Synopsys tools (ICC / ICC2 / ICV).
Experience doing physical verification for tile of chip physical design would be an asset.
Perl programming, TCL, SVRF, TVF programming not required, but would be advantages
IP / Standard cells layout design experience and exposure to Cadence is a plus.
Education Requirements :
Electrical / Computer / Biomedical / Mechanical Engineering Degree and / or Electronics related Diploma