Microchip, FPGA division is a leader in research, development and manufacturing of highly reliable non-volatile Field Programmable Gate Arrays.
The successful candidate will become member of an R&D team developing products within the framework of the software solution in the areas of Static Timing Analysis & Power Analysis.
Product development in these areas involves the core analysis engines built on a graph-like data structures, but also the addition of ease-of-use flows and features guiding customers in their analysis of their complex System-On-a-Chip (SOC) designs.
Primary Job Responsibilities :
The development of solutions tailored towards supporting very large SOC devices.
Run time improvements of Static Timing Analysis algorithms to suitable levels.
The enhancement of the timing constraint system with features such as coverage, verification, and auto-generation.
The modeling of ASIC blocks for timing using PrimeTime or other custom methods.
Improvement of the user experience through guidance tools and documentation support.
Secondary Job Responsibilities :
Integration of the timing engine and delay calculation into architecture evaluation flows
Development of a fast STA mode for integration into placement and routing algorithms
Participation to the R&D activities on subjects such as OCV, SSTA, IR Drop
Enforcement of Microchip’s Software Development Processes
Sustaining existing products and provide customer support
Required Qualifications :
MS Computer Science or Computer Engineering (or BS with additional experience)
7+ years of related experience
Experience in developing and maintaining complex software systems in C / C++ Proficient in developing scripts in Perl, Tcl, Python, etc.
Good understanding of graph theory.
Additional Qualifications :
Familiarity / knowledge / experience with any of the following would be a plus :
FPGA architectures, power analysis, Qt, AI-based applications.