Staff Design Engineer RTL IO PCIe
Advanced Micro Devices, Inc
Markham, CA
26d ago

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-

performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.

It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.

If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

In this exciting and challenging role, you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.

The NBIO organization designs new prototypes for cutting edge design challenges AMD is facing across all market segments.

The Design and Design Verification groups within this team are responsible for developing a balanced architecture between power consumption and performance, delivering high quality RTL code and creating advanced test benches using cutting edge verification techniques.

This is a temporary / contract role with options to extend and convert to full time.

The NBIO organization has great diversity of talent from all over the globe and works with other teams around the world.

You will learn from many senior team members while engaging and helping to shape the careers of newer engineers. This team is proud of its work and achievements and enjoys bringing on a new teammate to share in that success.

RESPONSIBILITIES :

  • Understand the architecture of DXIO (Distributed Cross Bar IP) and functional block being designed
  • As a Digital Design Engineer you will be responsible for developing RTL for protocol-specific PCS such as PCIe, SATA , etc.
  • Collaborating with analog design and system team to develop SerDes control algorithm.

  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
  • REQUIREMENTS :

  • Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-
  • out, and post-Si debug.

  • Have hands-on experience in Chiplevel Design / Integration activities.
  • Some Physical Design exposure required.
  • Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
  • Some exposure to DFT is a strong plus.
  • Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
  • Expertise in Perl and Tcl is a must.
  • Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
  • Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
  • Must have good communication & Analytical thinking skills.
  • Should have proficiency in flow development and scripting.
  • EDUCATION :

  • Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area
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